# AVL68K Hardware ## CPU and FPU At this time, AVL68K is designed specifically for the M68010 processor, however it is designed to be backward compatible if necessary with M68000 and forward compatible with the rest of the 68000 series. Note that individual implementations may choose which subset of this series to support. While M68010 does not explicitly support coprocessors, AVL68K allows for an optional M68881 or M68882 floating point unit to be used by software as a memory-mapped device. TBD: functions to use this may be provided in the KDLL, including with softfloat replacements. ## Memory map **Note** that this memory map, along with most things in this file, is only a suggestion. It is intended for use with 24-bit (16 MB) address space CPUs. The [boot process](68kos_core.md) is relatively hardware-agnostic, so the system may be configured for other setups. | From | To | Size | Name | |-------:|-------:|---------:|------------| | 000000 | 01FFFF | 128 kB | SUPER 0 | | 020000 | 03FFFF | 128 kB | SUPER 1 | | 040000 | 05FFFF | 128 kB | SUPER 2 | | 060000 | 07FFFF | 128 kB | SUPER 3 | | 080000 | 09FFFF | 128 kB | LARGE 4 | | 0A0000 | 0BFFFF | 128 kB | LARGE 5 | | 0C0000 | 0DFFFF | 128 kB | MPU | | 0E0000 | 0E3FFF | 16 kB | SMALL 0 | | 0E4000 | 0E7FFF | 16 kB | SMALL 1 | | 0E8000 | 0EBFFF | 16 kB | SMALL 2 | | 0EC000 | 0EFFFF | 16 kB | SMALL 3 | | 0F0000 | 0F3FFF | 16 kB | SMALL 4 | | 0F4000 | 0F7FFF | 16 kB | SMALL 5 | | 0F8000 | 0FBFFF | 16 kB | SMALL 6 | | 0FC000 | 0EFFFF | 16 kB | FPU | | 100000 | 1FFFFF | 1024 kB | SYSBUS | | 200000 | FFFFFF | 14366 kB | RAM | `SUPER 0` through `SUPER 3` contain the supervisor, up to 512 kB. If less space is needed, blocks may be repurposed as `LARGE 1` through `LARGE 3`. `MPU` is reserved for the memory protection unit, and FPU for an optional memory-mapped 68881 or 68882 floating-point unit. The remaining LARGE and SMALL blocks may be mapped to any memory or IO devices desired. System RAM should generally be aligned to the end of the `RAM` area, however a hole at the end of this region is permitted (allowing the use of RAM devices that place configuration registers here). The [boot process documentation](68kos_core.md) documents how the operating system is made aware of the valid RAM area. SUPER 0 contains the special Boot Console at the final 32-bit word at address `01FFFC`. Boot diagnostic info from the early loader is written to this location in ASCII one character at a time, specifically at the low byte `01FFFF` (though the entire dword is reserved, and the high byte in the 16-bit word is used for commands). Debuggers may intercept these writes and report them to the user. The hardware implementation must permit writes to this address (and may permit them to the entirety of `SUPER n`), though these writes do not need to be functional if the supervisor is located in true ROM. They must result in an assertion of DTACK, not BERR. It is recommended, though not mandatory, for the superfs builder to reserve the FAT cluster containing this address. This ensures no real code will go here, so in a debug system where the system "ROM" is emulated in RAM it is possible to write breakpoints into the code. To avoid wasting an entire cluster, a more sophisticated implementation might block executables from allocating the cluster but allow normal files. ### OAK bus controller OAK is a PLD used in the ICM68K reference design, and may be used to provide several system and bus control functions: - Decode of address (lines 14 through 23) into chip selects. - Decode and execution of MPU permission bits. - Decode of CPU space cycles into interrupt acknowledge and breakpoint signals. - Automatic address strobe wait state insertion for CEDAR, using asynchronous delay. - Bus error generation on invalid address ranges, preventing a hung bus (¹) - Optional clock divider providing system clock at one half of OAK's input clock (allowing faster peripherals). (¹) A bus timeout generator circuit is still recommended if any peripherals, including the external system bus, could be unresponsive to writes or reads, especially if userspace tasks are permitted to directly access them. ## Memory protection unit AVL68K contains a memory protection unit. The specific format and interface of this are left to the individual implementations, but it must be present. ICM68K, the reference implementation, uses the CEDAR memory protection unit; this MPU is recommended for systems with 24 bit address spaces. ### CEDAR MPU CEDAR has the following features (and caveats): - Supported access modes: none, read-only, read-write, read-execute. - Access mode defined for every 2kB block of address space, for each of up to 128 tasks. - Full readback of memory protection table supported. - Combinational design with sufficiently low propagation delay to permit zero wait state operation at or below 10 MHz, with automatic wait state insertion at higher bus speeds (with bus controller support, see OAK). - Open-collector bypass signal allows quick bypass for debugging, either with a single supervisor-mode write to the Task Select Register or with a hardware switch. - (Caveat) No automatic reset on boot — bus control logic must know to disregard MPU permission bits when operating in supervisor mode, otherwise MPU could interfere with startup. This is implemented by OAK. - (Caveat) Nonlinear access function for supervisor writes and reads; address bits are swizzled to simplify logic hardware. ## Large address space extension, for future definition A system with only 16 MB of address space may be able to support more RAM by using the MPU task select register to also select a page of RAM to appear in the RAM space, such that each task is still limited to 14 MB RAM but may have some of that independent from the rest. The details of this are TBD and may never be implemented.